1. Field of the Invention
The present invention relates to a method of manufacturing semiconductor devices and, more particularly, to an improvement on forming an interlayered insulating layer of semiconductor devices having a multi-layered wiring layer structure.
2. Description of the Related Art
With an increase in packing density of semiconductor devices, a multi-layered wiring structure in which a number of wiring layers are formed on a semiconductor substrate has been developed, and the number of steps of structuring such multi-layered wiring layers has increased.
In particular, a large part of manufacturing cost is occupied by the steps of forming multi-layered wiring layers. In order to reduce the cost of semiconductor devices, a reduction of the steps of forming multi-layered wiring layers has been demanded.
Conventional steps of forming multi-layered wiring layers will be described below. A first wiring material for lower wiring layers is deposited on a semiconductor substrate, and then, the deposited wiring material layer is patterned to form a plurality of lower wirings. A first insulating layer is formed on the lower wiring layers to bury the gaps between the lower wirings. At this time, step configuration is present on the surface of the first insulating film depending on the lower wiring pattern. The step configuration adversely affects to deposition of a second wiring material for an upper wiring layer and patterning of the upper wiring material layer, which are carried out in the following steps, so that serious defects such as disconnection or short circuit of the upper wirings may occur.
In general, before the second wiring material is deposited on the first insulating layer serving as an underlying layer, the surface of the first insulating film is flattened by etch back to remove the step configuration, and the second insulating material is deposited on the flattened surface of the first insulating layer.
Therefore, the conventional method of forming the interlayered insulating layer structure in which the first and second insulating films are superposed include an increased number of steps, i.e., formation of the first insulating film, flattening of the surface of the first insulation film, and formation of the second insulating film. This is a large hindrance to the demand for the reduction of the steps of forming the multi-layered wiring layers.
In place of the method of flattening the surface of the first insulating film, a method of moderating the step configuration on the surface of the first insulating film by forming an SOG (Spin on Glass) film of an insulating material on the first insulating film is available.
However, this method requires an increased number of annealing steps of forming of the SOG film. Furthermore, an undesired portion of the SOG film must be removed by etch back to assure the reliability of the upper wiring layer. As a result, the method requires an increased number of steps, and does not sufficiently cope with the demand for the reduction of the steps of forming multi-layered wiring layers.
Recently, as one of techniques coping with the reduction of the steps of forming multi-layered wiring layers, the following method has attracted attention. That is, in formation of an interlayered insulating layer on the lower wiring layers, an SiH.sub.4 gas reacts to H.sub.2 O.sub.2 (hydrogen peroxide water) serving as an oxidant at a low temperature (e.g., about 0.degree. C.) in a vacuum state to form a self-flow type (reflow) insulating film (to be referred to as a reflow insulating film hereinafter) on the lower wiring layer.
According to this method, the formation of an insulating film (reflow insulating film) and flattening of the surface of the insulating film can be simultaneously achieved. That is, in the step of forming the insulating film, film formation and flattening can be simultaneously achieved. For this reason, a reduction of the steps of forming multi-layered wiring layers can be realized.
However, in the method of forming the reflow insulating film, as is apparent from its reaction manner, moisture (H.sub.2 O) is generated during formation of the insulating film, and thus the insulating film has a high moisture content. The reflow insulating film tends to crack mainly when it is subjected to annealing (e.g., at 450.degree. C. for 30 minutes) at a later step.
FIG. 6 shows data obtained by actually measuring the state wherein cracks are formed in the reflow SiO.sub.2 film formed by the conventional method. In this case, the thickness of the reflow SiO.sub.2 film and the thickness of an SiO film (to be referred to as a cap film hereinafter) formed on the reflow SiO.sub.2 film by a general plasma CVD (Chemical Vapor Deposition) method are used as parameters. Upon completion of the film formation, these films are annealed at 450.degree. C. for 30 minutes.
As is apparent from FIG. 6, regardless of the presence/absence of the cap film, cracks are formed when the thickness of the reflow SiO.sub.2 film is 1.1 .mu.m or more. In other words, the allowable thickness of the reflow SiO.sub.2 film has an upper limit from the view point of crack resistance. The upper limit is as low as 1.0 .mu.m.
However, in order to form a reflow SiO2 film which is sufficiently flattened, the reflow SiO.sub.2 requires a thickness of a considerable extent.
When the cap film is formed on the reflow SiO.sub.2 film by a general plasma CVD, a semiconductor wafer is not still sufficiently heated up. For this reason, a cap film having a low wet etching rate is formed. Since the etching rate of the cap film is low, an abnormal configuration is formed between the cap film and the reflow SiO.sub.2 film in an etching step performed upon completion of the step of forming a cap film, for forming a through-hole or a via-hole in the reflow SiO.sub.2 film and the cap film. The abnormal configuration degrades the coverage of an upper wiring layer formed in the following step, and causes a connection failure of the upper wiring layer.
As described above, the thickness of a reflow SiO.sub.2 film obtained when a reflow insulating film forming technique is applied to the steps of forming an interlayered insulating layer of the conventional steps of forming multi-layered wiring layers is to be increased to flatten the reflow SiO.sub.2 film, however, the upper limit of the thickness is inadvantageously suppressed to a low level from a viewpoint of crack resistance.
In addition, an abnormal configuration is formed between the cap film and the reflow SiO.sub.2 film in an etching step for forming a through-hole or a via-hole in the reflow SiO.sub.2 film and the cap film formed thereon. The abnormal configuration degrades the coverage of the upper wiring layer, and causes a connection failure of the upper wiring layer.